CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies

by Gurjeet Kaur, Gurmohan Singh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 88 - Number 7
Year of Publication: 2014
Authors: Gurjeet Kaur, Gurmohan Singh
10.5120/15368-3878

Gurjeet Kaur, Gurmohan Singh . Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies. International Journal of Computer Applications. 88, 7 ( February 2014), 44-49. DOI=10.5120/15368-3878

@article{ 10.5120/15368-3878,
author = { Gurjeet Kaur, Gurmohan Singh },
title = { Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies },
journal = { International Journal of Computer Applications },
issue_date = { February 2014 },
volume = { 88 },
number = { 7 },
month = { February },
year = { 2014 },
issn = { 0975-8887 },
pages = { 44-49 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume88/number7/15368-3878/ },
doi = { 10.5120/15368-3878 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:07:03.079995+05:30
%A Gurjeet Kaur
%A Gurmohan Singh
%T Analysis of Low Power CMOS Current Comparison Domino Logic Circuits in Ultra Deep Submicron Technologies
%J International Journal of Computer Applications
%@ 0975-8887
%V 88
%N 7
%P 44-49
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Performance of high fan–in Domino circuits is degraded by technology scaling due to exponential increase in leakage. To improve the performance Current Comparison Domino (CCD) circuits are widely used. This work presents design of wide fan-in high performance current comparison domino circuits with goals of minimizing the power dissipation and propagation delay at 90nm and 45nm ultra deep submicron (UDSM) technology nodes. A Current Comparison Domino (CCD) 32-input wide footless OR gate circuit is employed for design and analysis work. Cadence GPDK 90nm & 45nm model parameters are used in this research work. Cadence Virtuoso schematic editor is used to draw the schematic and Spectre circuit simulator is used for simulation work. Layouts are generated in Virtuoso Layout editor. Pre-layout and post- layout simulation results are compared for validation of results. At 45nm technology, the Power consumption is 718. 6nW, Propagation delay is 1. 450ns and Power delay product (PDP) is 1. 041fj. 92% improvement in power consumption at 45nm technology has been achieved as compared to previous work (at 16nm) by generating highly customized layout of the designed circuit.

References
  1. J. M. Rabaey, A. Chandrakasan, and B. Nicolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2003.
  2. Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 3rd Edition, Tata McGraw-Hill Publishing Company Ltd, New Delhi, 2007.
  3. Neil H. E. Weste and K. Eshragian, Principle of CMOS VLSI Design, 2nd Edition, Pearson Education (Asia) Pvt. Ltd. 2000.
  4. Wayne Wolf, Modern VLSI Design: IP-Based Design, 4thEdition, Pearson Education, 2008.
  5. Ali Peiravi and Md. Asyaei, "Current-Comparison-Based Domino: New Low–Leakage High –Speed Domino Circuit for Wide Fan –In Gates", IEEE Transactions Very Large Scale Integration (VLSI) Systems, vol. 21, no. 99, pp 934-943, May 2012.
  6. Sarma, D. S. V. S. , Mahapatra, K. K. , "Improved techniques for high performance noise-tolerant domino CMOS logic circuits," Students Conference on Engineering and Systems (SCES), pp. 1-6 March 2012.
  7. Digital object Identifier:10. 1109/SCES. 2012. 6199119
  8. H. F. Dadgour and K. Banerjee, "A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates," IEEE Transactions Very Large Scale Integration (VLSI) Systems, vol. 18, no. 11, pp. 1567-1577, Nov. 2010.
  9. Sharroush, S. M. , Abdalla, Y. S. , Dessouki, A. A. , El-Badawy, E. -S. A. , "Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper," Computer and Communication Engineering, 2008. ICCCE 2008. International Conference on Electronic Design, pp. 633-637, 13-15 May 2008.
  10. Digital object Identifier: 10. 1109/ICCCE. 2008. 4580681
  11. H. Mahmoodi and K. Roy, "Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style," IEEE Transactions Circuits and Systems I: Regular Papers, vol. 51, no. 3, pp. 495-503, March 2004
Index Terms

Computer Science
Information Sciences

Keywords

Dynamic logic Static logic Domino logic UDSM CCD

Powered by PhDFocusTM